搜索资源列表
dig_watch
- fpga实验，基于VHDL语言的数字跑表设计，其中包含有存储模块。-Fpga experiment, the digital stopwatch designed based on VHDL language, which contains a storage module.
FPGA
- 韩福柱老师FPGA实验源码，用vhdl语言在xilinx FPGA上实现，包括ad采集，温度传感器读取，秒表，跑马灯和按键次数统计4个实验-Han Fu teacher FPGA column experiment source code, vhdl languages on xilinx FPGA implementations, including ad acquisition, temperature sensor readings, stopwatch, marquees and key
clock
- 本个程序主要通过vhdl来实现一个秒表的设计-This procedure mainly through the VHDL to achieve a stopwatch design
333
- 课程设计设计主要使用了VHDL语言，采用的开发软件是Quartus-II，设计一个循环彩灯控制器和数字显示秒表。在Quartus-II开发平台下进行了编译、仿真。-Cycle lantern controller and digital display stopwatch
EDA-24秒倒计时程序
- 本秒表计时器用于体育竞赛及各种要求有较精确时的各领域。此计时器是用一块专用的芯片，用VHDL语言描述的。它除开关、时钟和显示功能以外，它还包括1/100s计时器所有的控制和定时功能，其体积小，携带方便。(The stopwatch timer is used in sports competitions and in various fields where requirements are more accurate. This timer is written in a VHDL langu
ise
- 在ise软件上，用VHDL语言，设计的数字跑表，可以两位计数，含分频器，计数器(In the ISE software, using VHDL language digital stopwatch design, can two counts, including frequency divider, counter)